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preliminary w29s201 128k 16 cmos flash memory with synchronous burst read publication release date: april 1999 - 1 - revision a1 general description the w29s201 is a 2-megabit, 5-volt only cmos flash memory organized as 128k 16 bits. the w29s201 supports both assynchronous & high performance synchronous burst read modes. the device can be programmed and erased in-system with a standard 5v power supply. a 12-volt v pp is not required. the unique cell architecture of the w29s201 results in fast program/erase operations with extremely low current consumption (compared to other comparable 5-volt flash memory products). the device can also be programmed and erased using standard eprom programmers. features single 5-volt operations: - 5-volt read - 5-volt erase - 5-volt program fast program operation: - word-by-word programming: 50 m s (max.) fast erase operation: 100 ms (typ.) fast synchronous burst read access time: 15/17 ns (typ.) high performance synchronous burst read mode up to 50mhz clock frequency support linear burst mode read with wrap- around feature. no burst length limitation. fast assynchronous random read access time: 45//55 ns endurance: 1k/10k cycles (min.) twenty-year data retention hardware data protection sector configuration - one 8k words boot block with lockout protection - two 8k words parameter blocks - one 104k words (208k bytes) main memory array blocks low power consumption - active current: 35 ma (typ.) - standby current: 20 m a (typ.) automatic program and erase timing with internal v pp generation end of program or erase detection - toggle bit - data polling latched address and data ttl compatible i/o jedec standard word-wide pinouts available packages: 48-pin tsop
preliminary w29s201 - 2 - pin configurations 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 dq15 a9 a10 a11 a12 a13 a14 a15 oe gnd 48-pin tsop 24 23 nc a16 we ce a7 a6 a5 a4 a3 a2 a1 a0 21 22 48 47 46 45 44 43 42 41 nc reset clk nc a8 dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 v cc dq7 dq14 dq6 dq13 dq5 dq12 dq4 gnd nc mode adv nc block diagram control output buffer decoder main memory 104k words ce/oe/we a0 . . a16 . . dq0 dq15 v dd v ss boot block 8k words parameter block2 8k words parameter block1 8k words 1ffff 06000 05fff 04000 03fff 02000 01fff 00000 reset adv/clk/mode pin description symbol pin name reset reset a0 - a16 address inputs dq0 - dq15 data inputs/outputs ce chip enable oe output enable we write enable adv address valid clk clock mode synch/assyn mode select v dd power supply gnd ground nc no connection
preliminary w29s201 publication release date: april 1999 - 3 - revision a1 functional description synchronous burst & asynchronous read mode features the winbond ?s w29s201 flash device requires 3 additional control pins for synchronous burst read operations: synchronous/assynchronous read mode select ( mode ), address valid ( adv ), and clock (clk). this synchronous read mode feature allows w29s201 to be interfaced easily to a wide range of dsp, microprocessors, micro-controllers for higher performance read operations. all these 3 pins are only activated internally when chip is selected ( ce =v il ). the mode input pin is used to select either synchronous or assynchronous read mode for the memory read operations. if mode is held low, the synchronous burst read mode is selected for the read operation, and if mode is held high then assynchronous read mode is selected for all read operations (the adv and clk are ignored by the flash internally). the adv input pin is used when the chip is selected in the synchronous read mode ( ce =v il and mode =v il ) to load the initial random address into the flash at the rising edge of the clock when adv =v il , and to increment the internal address counter at the rising edge of the clock when adv =v ih . the clk input pin can be tied to the system clock to provide the fundamental timing and array synchronous burst read operating frequency. both adv and clk inputs are only enabled when chip is selected to operate in the synchronous burst read mode ( ce =v il and mode =v il ). the mode input pin is internally pulled high for applications which does not require the synchronous burst read operations, hence allowing these additional 3 pins to be considered as the no connect (nc) pins. however, winbond recommends that these 3 pins be driven at known logic level externally if possible. the states of these 3 additional pins are ignored during all write operations. assynchronous random read mode the assynchronous read operation of the w29s201 is controlled by ce and oe , both of which have to be low for the host to obtain data from the outputs. ce is used for device selection. when ce is high, the chip is de-selected and only standby power will be consumed. oe is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either ce or oe is high. refer to the timing waveforms for further details. synchronous burst read mode beside being assynchronously controlled by ce and oe pins similarly as in the assynchronous read operations, the selected w29s201 flash device when used in synchronous burst read operation mode ( mode =v il ) requires the host to provide the initial random burst address by driving the adv pin low at the rising edge of the clock (clk) to latch the initial burst random address into the flash device. initial output data (at dq pins) become available 2 clock cycles (or 3 clock cycles depending on starting address, refer to the timing waveforms for further details). by driving the adv pin high at the rising edge of the clock enables the w29s201 device to read data from the next binary incremental address (linear burst mode). sequential output data becomes available t kqv (15/17) ns of burst access time after the rising edge of the clock (always 2 clk periods after the address increment started, i.e., adv pin went high). there is no burst length limitation for the w29s201 device architecture, hence allowing the host to sequentially read out the entire memory data (128k words) with just one burst read operation. the w29s201 also supports full memory array linear wrap-around mode. the w29s201q-45/55 can be used
preliminary w29s201 - 4 - to operate at a system clock frequency as high as 50/40mhz with only 3 initial wait-states (3-1-1-1) required for the initial random access depending on the host performance and capability on the starting & ending burst address. refer to the timing waveforms for further details. reset operation the reset input pin can be used in some application. when reset pin is at high state, the device is in normal operation mode. when reset pin is driven low for at least a period of t rp , it will halts the device and all outputs are at high impedance state. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to assure data integrity. as the high state re-asserted to the reset pin, the device will return to read or standby mode, it depends on the control signals. the system can read data t rh after the reset pin returns to v ih . the other function for reset pin is temporary reset the boot block. by applying the 12v to reset pin, the boot block can be reprogrammed even though the boot block lockout function is enabled. boot block operation there is one 8k-word boot block in this device, which can be used to store boot code. it is located in the first 8k words of the memory with the address range from 0000(hex) to 1fff(hex). see command codes for boot block lockout enable for the specific code. once this feature is set the data for the designated block cannot be erased or programmed (programming lockout); other memory locations can be changed by the regular programming method. once the boot block programming lockout feature is activated, the chip erase function will be disable. there is one condition that the lockout feature can be overrides. just apply 12v to reset pin, the lockout feature will temporary be inactivated and the block can be erased/programmed. once the reset pin returns to ttl level, the lockout feature will be activated again. in order to detect whether the boot block feature is set on the 8k-words block, users can perform software command sequence: enter the product identification mode (see command codes for identification/boot block lockout detection for specific code), and then read from address "0002 hex". if the output data in dq0 is "1", the boot block programming lockout feature is activated; if the output data in dq0 is "0", the lockout feature is inactivated and the block can be erased or programmed. to return to normal operation, perform a three-byte command sequence (or an alternate single-word command) to exit the identification mode. for the specific code, see command codes for identification/boot block lockout detection. chip erase operation the chip-erase mode can be initiated by a six-word command sequence. after the command loading cycle, the device enters the internal chip erase mode, which is automatically timed and will be completed in a fast 100 ms (typical). the host system is not required to provide any control or timing during this operation. the entire memory array will be erased to ff(hex). by the chip erase operation if the boot block programming lockout feature is not activated. once the boot block lockout feature is activated, the chip erase function will be disable. the device will automatically return to normal read mode after the erase operation completed. data polling and/or toggle bits can be used to detect end of erase cycle.
preliminary w29s201 publication release date: april 1999 - 5 - revision a1 sector erase operation the three sectors, main memory and two parameters blocks, can be erased individually by initiating a six-word command sequence. sector address is latched on the falling we edge of the sixth cycle while the 30(hex) data input command is latched at the rising edge of we. after the command loading cycle, the device enters the internal sector erase mode, which is automatically timed and will be completed in a fast 100 ms (typical). the host system is not required to provide any control or timing during this operation. the device will automatically return to normal read mode after the erase operation completed. data polling and/or toggle bits can be used to detect end of erase cycle. when the boot block lockout feature is inactivated, the boot block and the main memory block will be erased together. once the boot block is locked, only the main memory block will be erased by the execution of sector erase operation. program operation the w29s201 is programmed on a word-by-word basis. program operation can only change logical data "1" to logical data "0" the erase operation (changed entire data in main memory and/or boot block from "0" to "1" is needed before programming. the program operation is initiated by a 4-word command cycle (see command codes for word programming). the device will internally enter the program operation immediately after the word-program command is entered. the internal program timer will automatically time-out (50 m s max. - t bp ) once completed and return to normal read mode. data polling and/or toggle bits can be used to detect end of program cycle. hardware data protection the integrity of the data stored in the w29s201 is also hardware protected in the following ways: (1) noise/glitch protection: a we pulse of less than 15 ns in duration will not initiate a write cycle. (2) v dd power up/down detection: the programming operation is inhibited when v dd is less than 2.5v typical. (3) write inhibit mode: forcing oe low, ce high, or we high will inhibit the write operation. this prevents inadvertent writes during power-up or power-down periods. (4) v dd power-on delay: when v dd has reached its sense level, the device will automatically time-out 5 ms before any write (erase/ program) operation. data polling (dq 7 )- write status detection the w29s201 includes a data polling feature to indicate the end of a program or erase cycle. when the w29s201 is in the internal program or erase cycle, any attempt to read dq 7 of the last word loaded will receive the complement of the true data. once the program or erase cycle is completed, dq 7 will show the true data. note that dq 7 will show logical "0" during the erase cycle, and become logical "1" or true data when the erase cycle has been completed. note that is for assynchronous read mode only ( mode =v ih ). toggle bit (dq 6 )- write status detection in addition to data polling, the w29s201 provides another method for determining the end of a program cycle. during the internal program or erase cycle, any consecutive attempts to read dq 6 will produce alternating 0's and 1's. when the program or erase cycle is completed, this toggling between 0's and 1's
preliminary w29s201 - 6 - will stop. the device is then ready for the next operation. note that is for assynchronous read mode only ( mode =v ih ). product identification the product id operation outputs the manufacturer code and device code. programming equipment automatically matches the device with its proper erase and programming algorithms. the manufacturer and device codes can be accessed by software or hardware operation. in the software access mode, a six-word (or jedec 3-word) command sequence can be used to access the product id. a read from address 0000h outputs the manufacturer code, 00da(hex). a read from address 0001(hex) outputs the device code, 0fae(hex). the product id operation can be terminated by a three-word command sequence or an alternative one-word command sequence (see command definition table). in the hardware access mode, access to the product id is activated by forcing ce and oe low, we high, and raising a9 to 12 volts. note that is for assynchronous read mode only ( mode =v ih ).
preliminary w29s201 publication release date: april 1999 - 7 - revision a1 absolute maximum ratings parameter rating unit power supply voltage to v ss potential -0.5 to +7.0 v operating temperature 0 to +70 c storage temperature -65 to +150 c d.c. voltage on any pin to ground potential except a9 -0.5 to v dd +1.0 v transient voltage (<20 ns ) on any pin to ground potential -1.0 to v dd +1.0 v voltage on a9 pin to ground potential -0.5 to 12.5 v note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. the above ratings are for maximum stress ratings only, functional operation under these conditions or at any other condition beyond those indicated in the operational sections of this datasheet is not implied. table of operating modes operating mode selection (v hh = 12v 0.5v) mode pins ce oe we reset mode adv clk address dq. latch burst address v il x v ih v ih v il v il a in high z/d out burst address increment read v il v il v ih v ih v il v ih x d out read (assyn.) v il v il v ih v ih v ih x x a in dout erase/program v il v ih v il v ih x x x a in din standby v ih x x v ih x x x x high z erase/program x v il x v ih x x x x high z/d out inhibit x x v ih v ih x x x x high z/d out output disable x v ih x v ih x x x x high z product id (assyn. read) v il v il v ih v ih v ih x x a0 = v il ; a1 - a15 = v il ; a9 = v hh manufacturer code 00da (hex) v il v il v ih v ih v ih x x a0 = v ih ; a1 - a15 = v il ; a9 = v hh device code 0fae (hex) reset x x x v il x x x x high z
preliminary w29s201 - 8 - table of command definition command no. of 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle description cycles addr. data addr. data addr. data addr. data addr. data addr. data read 1 a in d out chip erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 10 main memory erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 sa 30 word program 4 5555 aa 2aaa 55 5555 a0 a in d in boot block lockout 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 40 product id entry 3 5555 aa 2aaa 55 5555 90 product id exit (1) 3 5555 aa 2aaa 55 5555 f0 product id exit (1) 1 xxxx f0 note: 1. address format: a14 - a0 (hex); data format: dq15 - dq8 (don't care); dq7-dq0 (hex) 2. either one of the two product id exit commands can be used. 3. sa : sector address sa = 03xxxh for parameter block1 s a = 05xxxh for parameter block2 sa = 1fxxxh - for main memory block when boot block lockout feature is activated - for both boot block and main memory block when boot block lockout feature is inactivated
preliminary w29s201 publication release date: april 1999 - 9 - revision a1 command codes for word program word sequence address data 0 write 5555h aah 1 write 2aaah 55h 2 write 5555h a0h 3 write programmed-address programmed-data pause t bp word program flow chart word program command flow load data aa to address 5555 load data 55 to address 2aaa load data a0 to address 5555 load data din to programmed- address exit pause t bp notes for software program code: data format: dq15 - dq8: don't care ; dq7-dq0(hex) address format: a14 - a0 (hex)
preliminary w29s201 - 10 - command codes for chip erase byte sequence address data 1 write 5555h aah 2 write 2aaah 55h 3 write 5555h 80h 4 write 5555h aah 5 write 2aaah 55h 6 write 5555h 10h pause t ec chip erase acquisition flow load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa exit load data 10 to address 5555 pause t ec notes for chip erase: data format: dq15-dq8: don't care ; dq7 - dq0 (hex) address format: a14 - a0 (hex)
preliminary w29s201 publication release date: april 1999 - 11 - revision a1 command codes for sector erase byte sequence address data 1 write 5555h aah 2 write 2aaah 55h 3 write 5555h 80h 4 write 5555h aah 5 write 2aaah 55h 6 write sa* 30h pause t ec sector erase acquisition flow load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 30 to address sa* exit pause t ec notes for chip erase: data format: dq15-dq8: don't care ; dq7 - dq0 (hex) address format: a14 - a0 (hex) sa = 03xxx for parameter block1 sa = 05xxx for parameter block2 sa = 1fxxx - for main memory block when boot block lockout feature is activated - for both boot block and main memory block when boot block lockout feature is inactivated
preliminary w29s201 - 12 -
preliminary w29s201 publication release date: april 1999 - 13 - revision a1 command codes for product identification and boot block lockout detection byte sequence alternate product (6) identification/boot block lockout detection entry software product identification/boot block lockout detection exit (7) address data address data 1 write 5555 aa 5555h aah 2 write 2aaa 55 2aaah 55h 3 write 5555 90 5555h f0h pause 10 m s pause 10 m s software product identification and boot block lockout detection acquisition flow product identification entry (1) load data 55 to address 2aaa load data 90 to address 5555 pause 10 s product identification and boot block lockout detection mode (3) read address = 0000 data = 00da read address = 0001 data = 0fae read address = 0002 data in dq0 =1/0 (4) product identification exit(7) load data 55 to address 2aaa load data f0 to address 5555 normal mode (5) (2) (2) load data aa to address 5555 m load data aa to address 5555 pause 10 s m notes for software product identification/boot block lockout detection: (1) data format: dq15-dq8 (don't care), dq7 - dq0 (hex); address format: a14 - a0 (hex) (2) a1 - a16 = v il ; manufacture code is read for a0 = v il ; device code is read for a0 = v ih . (3) the device does not remain in identification and boot block lockout detection mode if power down. (4) if the output data in dq0 = 1, the boot block programming lockout feature is activated; if the output data in dq0 = 0, the lockout feature is inactivated and the block can be programmed. (5) the device returns to standard operation mode. (6) optional 1-write cycle (write f0 hex at xxxx address) can be used to exit the product identification/boot block lockout detection.
preliminary w29s201 - 14 - command codes for boot block lockout enable byte sequence boot block lockout feature set address data 1 write 5555h aah 2 write 2aaah 55h 3 write 5555h 80h 4 write 5555h aah 5 write 2aaah 55h 6 write 5555h 40h pause t ec boot block lockout enable acquisition flow boot block lockout feature set flow load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 40 to address 5555 exit pause t ec notes for boot block lockout enable: data format: dq15-dq8 don't care), dq7 - dq0 (hex) address format: a14 - a0 (hex)
preliminary w29s201 publication release date: april 1999 - 15 - revision a1 dc characteristics dc operating characteristics (v dd = 5.0v 10 % , v ss = 0v, t a = 0 to 70 c) parameter sym. test conditions limits unit min. typ. max. v dd assyn. read current i ccr1 ce = oe =v il , we =v ih , mode =v ih, all dqs open, clk & adv = v il /v ih , address inputs =v il /v ih at f = 5 mhz - 35 75 ma v dd synch burst read current i ccr2 ce = oe =v il , we =v ih , mode =v il , all dqs open, adv =v il /v ih , address inputs =v il /v ih, clk at f = f clk (max.) - - 175 ma v dd erase or program current i ccw erase or program operation in progress, all dqs open. - - 50 ma standby v dd current (ttl input) i sb 1 ce = v ih , all dqs open other inputs = v il /v ih - 2 3 ma standby v dd current (cmos input) i sb 2 ce = v dd 0.3v, all dqs open other inputs = gnd 0.3v or v dd 0.3v - 20 200 m a input leakage current i li v in = gnd to v dd - - 10 m a output leakage current i lo v out = gnd to v dd - - 10 m a input low voltage v il - -0.3 - 0.8 v input high voltage v ih - 2.0 - v dd +0.5 v output low voltage v ol i ol = 2.1 ma - - 0.45 v output high voltage v oh i oh = -0.4 ma 2.4 - - v
preliminary w29s201 - 16 - power-up timing parameter symbol typical unit power-up to read operation t pu . read 100 m s power-up to write operation t pu . write 5 ms capacitance (v dd = 5.0v, t a = 25 c, f = 1 mhz) parameter symbol conditions max. unit i/o pin capacitance c i/o v i/o = 0v 12 pf input capacitance c in v in = 0v 6 pf ac characteristics ac test conditions parameter conditions input pulse levels 0v to 3.0v input rise/fall time < 5 ns input/output timing level 1.5v/1.5v output load 1 ttl gate and c l = 30 pf ac test load and waveform +5v 1.8k 1.3k d out w w 30 pf (including jig and scope) input 3v 0v test point test point 1.5v 1.5v output
preliminary w29s201 publication release date: april 1999 - 17 - revision a1 assynchronous read cycle timing parameters (v cc = 5.0v 10 % , v cc = 0v, t a = 0 to 70 c) parameter sym. w29s201-45 w29s201-55 unit min. max. min. max. read cycle time t rc 45 - 55 - ns chip enable access time t ce - 45 - 55 ns address access time t aa - 45 - 55 ns output enable access time t oe - 25 - 30 ns ce low to active output t clz 0 - 0 - ns oe low to active output t olz 0 - 0 - ns ce high to high-z output t chz - 20 - 25 ns oe high to high-z output t ohz - 20 - 25 ns output hold time t oh 0 - 0 - ns note: the parameter of t clz , t olz , t chz , t ohz are characterized only and is not 100% tested. synchronous burst read cycle timing parameters (v cc = 5.0v 10 % , v cc = 0v, t a = 0 to 70 c) parameter sym. w29s201-45 w29s201-55 unit min. max. min. max. clk frequency f clk - 50 - 40 mhz clk period t cyc 20 - 25 - ns clk high time t kh 7 - 8 - ns clk low time t kl 7 - 8 - ns clk rise time t klh - 2 - 3 ns clk fall time t khl - 2 - 3 ns ce setup time to clk t ces 15 - 20 - ns address setup time to clk t aks 12 - 15 - ns address hold time from clk t akh 2 - 2 - ns adv setup time to clk t advs 12 - 15 - ns adv hold time from clk t advh 2 - 2 - ns mode setup time to clk t mods 15 - 20 - ns mode hold time from clk t modh 5 - 5 - ns clk to valid output t kqv - 15 - 17 ns output hold time from clk t kqh 1 - 1 - ns
preliminary w29s201 - 18 - note: the parameter of t kqh is characterized only and is not 100% tested.
preliminary w29s201 publication release date: april 1999 - 19 - revision a1 ac characteristics, continued write cycle timing parameters parameter symbol min. typ. max. unit address setup time t as 0 - - ns address hold time t ah 50 - - ns we and ce setup time t cs 0 - - ns we and ce hold time t ch 0 - - ns oe high setup time t oes 0 - - ns oe high hold time t oeh 0 - - ns ce pulse width t cp 70 - - ns we pulse width t wp 70 - - ns we high width t wph 100 - - ns data setup time t ds 50 - - ns data hold time t dh 10 - - ns word programming time t bp - 10 50 m s erase cycle time t ec - 0.1 1 s note: all ac timing signals observe the following guidelines for determining setup and hold times: (a) high level signal 's reference level is v ih and (b) low level signal's reference level is v il . data polling and toggle bit timing parameters parameter sym. w29s201-45 w29s201-55 unit min. max. min. max. oe to data polling output delay t oep - 25 - 30 ns ce to data polling output delay t cep - 45 - 55 ns oe to toggle bit output delay t oet - 25 - 30 ns ce to toggle bit output delay t cet - 45 - 55 ns hardware reset timing parameters parameter sym. min. max. unit reset pin low to read or write t ready - 500 ns reset pulse width t rp 500 - ns
preliminary w29s201 - 20 - reset high time before read(1) t rh 50 - ns note: 1. the parameters are characterized only and is not 100% tested.
preliminary w29s201 publication release date: april 1999 - 21 - revision a1 timing waveforms synchronous burst read cycle timing 1 (3-1-1-1 linear mode) (starting address is even and ending address is odd) t cyc clk t advs t advh t kah 2n 2k t ces t kqh high-z adv mode a[16:0] ce oe dq[15:0] don't care undefined t aks 2n+2 2n+1 2n+3 2k 2k+1 t olz t clz t oh t kqv t mods 2n load burst address increment address counter t kqv t modh 2k+2 2k+3 t advh t advs (starting address is even 2n) t kqv 2n 2n+1 2n+2 2n+3 2k 2k 2k+1 2k+2 2k+3 load burst address (starting address is even 2k) ending burst addr. is odd (2n+3) dq's valid 2 clk periods after loading (adv=low) dq's valid 2 clk periods after loading (adv=low) next dq's valid 2 clk periods after increment (adv=hi) note : the above waveform is applicable to synchronous read mode with starting random address is always even and ending address is always odd address only. the adv can be 1 clk period pulse minimum, and the total wait states can be 3 clk periods minimum. initial output data dq ?s become valid 2 clk periods after the valid address loading started ( adv =low) & next sequential output data dq ?s become valid 2 clk periods after address increment started ( adv =hi).
preliminary w29s201 - 22 - synchronous burst read cycle timing 2 (4-1-1-1 linear mode) (starting address & ending address are both either even or odd) t cyc clk t advs t advh t kah 2n+1 2k+1 t ces high-z adv mode a[16:0] ce oe dq[15:0] don't care undefined t aks 2n+2 2n+1 2n+3 2k+1 2k+2 t olz t clz t oh t kqv t mods t kqh load burst address increment address counter t kqv t modh 2k+3 t advh t advs (starting address is odd 2n+1) t kqv 2n+1 2n+2 2n+3 2k+1 2k+1 2k+2 load burst address (starting address is odd 2k+1) ending addr. is odd (2n+3) dq's valid 3 clk periods 2n+1 2k+1 2k+3 after valid loading (adv=low) dq's valid 3 clk periods after valid loading (adv=low) next dq's valid 2 clk periods after increment (adv=hi) note : the above waveform is applicable to synchronous burst read mode with starting random address and ending burst address are both either even or odd only (shown above with starting & ending are odd address). the adv must be minimum 2 clk period pulse, and the total wait states hence can be 4 clk periods minimum. initial output data dq ?s become valid 3 clk periods after the valid address loading started ( adv =low) & next sequential output data dq ?s become valid 2 clk periods after address increment started ( adv =hi).
preliminary w29s201 publication release date: april 1999 - 23 - revision a1 synchronous burst read cycle timing 3 (5-1-1-1 linear mode) (starting address & ending address can be any random address) t cyc clk t advs t advh t kah n k t ces high-z adv mode a[16:0] ce oe dq[15:0] don't care undefined t aks n+1 n n+2 k k+1 t olz t clz t kqv t mods t kqh load burst address (n) increment address counter t kqv t advh t advs t kqv n n n+1 n+3 k load burst address (k) dq's valid 3 clk periods n n+2 after valid loading (adv=low) dq's valid 3 clk periods after valid loading (adv=low) k k k+1 k+2 k+3 n+3 next dq's valid 2 clk periods after increment (adv=hi) k note : the above waveform is applicable to synchronous burst read mode with any starting random address and any ending burst (can be either even or odd). the adv must be minimum 3 clk period pulse, and the total wait states hence can be 5 clk periods minimum. initial output data dq ?s become valid 3 clk periods after the valid address loading started ( adv =low) & next sequential output data dq ?s become valid 2 clk periods after address increment started ( adv =hi). clock input timing diagram clk t cyc t kl t kh 10% 90% 0v 3v t klh t khl
preliminary w29s201 - 24 - assynchronous read cycle timing diagram address a16-0 dq15-0 data valid data valid high-z ce oe we t rc v ih t clz t olz t oe t ce t oh t aa t chz t ohz high-z we controlled command write cycle timing diagram address a16-0 dq15-0 data valid ce oe we t as t cs t oes t ah t ch t oeh t wph t wp t ds t dh
preliminary w29s201 publication release date: april 1999 - 25 - revision a1 timing waveforms, continued ce controlled command write cycle timing diagram high z data valid ce oe we dq15-0 t as t ah t cph t oeh t dh t ds t cp t oes address a16-0 program cycle timing diagram address a16-0 word 0 word 1 word 2 internal write start dq15-0 ce oe we word program cycle t bp t wph t wp 5555 5555 2aaa aa a0 55 address data-in word 3
preliminary w29s201 - 26 - timing waveforms, continued data polling timing diagram address a16-0 dq7 we oe ce x x x x t cep t oeh t oep t oes t ec t bp or toggle bit timing diagram address a16-0 dq6 ce oe we t oeh t oes t bp or t ec
preliminary w29s201 publication release date: april 1999 - 27 - revision a1 timing waveforms, continued boot block lockout enable timing diagram sw23 sw1 sw0 address a16-0 dq15-0 ce oe we sw3 sw4 sw5 six-word code for boot block lockout feature enable t ec t wp t wph 5555 2aaa 5555 5555 2aaa 5555 xxaa xx55 xx80 xxaa xx55 xx40 chip erase timing diagram sw2 sw1 sw0 address a16-0 dq15-0 ce oe we sw3 sw4 sw5 internal erase starts six-word code for 5v-only software chip erase t wp t wph t ec 5555 2aaa 5555 5555 2aaa 5555 xxaa xx55 xx80 xxaa xx55 xx10
preliminary w29s201 - 28 - timing waveforms, continued sector erase timing diagram sw2 sw1 sw0 address a16-0 dq15-0 ce oe we sw3 sw4 sw5 internal erase starts six-word code for 5v-only software main memory erase t wp t wph t ec 5555 2aaa 5555 5555 2aaa sa xxaa xx55 xx80 xxaa xx55 xx30 sa = sector address reset timing diagram ce oe reset t rh t t ready rp
preliminary w29s201 publication release date: april 1999 - 29 - revision a1 ordering information part no. access time ( n s) power supply current max. ( m a) standby v dd current max. ( m a) package cycle w29s201t-45 45 75 200 (cmos) 48-pin tsop (12 mm 20 mm) 1k W29S201T-55 55 75 200 (cmos) 48-pin tsop (12 mm 20 mm) 1k w29s201t-45b 45 75 200 (cmos) 48-pin tsop (12 mm 20 mm) 10k W29S201T-55b 55 75 200 (cmos) 48-pin tsop (12 mm 20 mm) 10k notes: 1. winbond reserves the right to make changes to its products without prior notice. 2. purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
preliminary w29s201 - 30 - package dimensions 48-pin tsop (12 mm 20 mm) e 1 48 b e d y a1 a a2 l1 l c h d 0.020 0.004 0.007 0.037 0.002 min. 0.60 y l l1 c 0.50 0.10 0.70 0.21 dimension in mm a a2 b a1 0.95 0.17 0.05 symbol min. 1.20 0.27 1.05 1.00 0.22 max. nom. 0.028 0.008 0.024 0.011 0.041 0.047 0.009 0.039 nom. dimension in inches max. e h d 0 5 0 5 e d 18.3 18.4 18.5 19.8 20.0 20.2 11.9 12.0 12.1 0.720 0.724 0.728 0.780 0.787 0.795 0.468 0.472 0.476 0.10 0.80 0.031 0.004 0.020 0.50 q q
preliminary w29s201 publication release date: april 1999 - 31 - revision a1 version history version date page description a1 apr. 1999 advance information only, some parameters & waveforms are to be determined. headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5796096 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-27197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-27190505 fax: 886-2-27197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics corporation america corp. 2727 n. first st., san jose, ca 95134, u.s.a. tel: 408-9436666 fax: 408-5441798 note: all data and specifications are subject to change without notice.

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